Board:amd/olivehillplus

From coreboot
Jump to: navigation, search

This page describes how to use coreboot on the FT3b Olive Hill Plus mainboard.

Status

Device/functionality Status Comments
CPU
CPU works OK
L1 cache enabled OK
L2 cache enabled OK
L3 cache enabled N/A
Multiple CPU support N/A
Multi-core support OK
Hardware virtualization Untested
RAM
EDO N/A
SDRAM N/A
SO-DIMM N/A
DDR N/A
DDR2 N/A
DDR3 OK unbuffered
Dual channel support OK
ECC support OK
On-board Hardware
On-board IDE 3.5" N/A
On-board IDE 2.5" Unknown
On-board SATA OK
On-board SCSI N/A
On-board USB OK
On-board VGA OK
On-board Ethernet OK
On-board Audio OK
On-board Modem N/A
On-board FireWire N/A
On-board Smartcard reader N/A
On-board CompactFlash N/A
On-board PCMCIA N/A
On-board Wifi N/A
On-board Bluetooth N/A
On-board SD card reader N/A
Add-on slots/cards
ISA add-on cards N/A
Audio/Modem-Riser (AMR/CNR) cards N/A
PCI add-on cards N/A
Mini-PCI add-on cards OK
PCI-X add-on cards N/A
AGP graphics cards N/A
PCI Express x1 add-on cards N/A
PCI Express x2 add-on cards N/A
PCI Express x4 add-on cards OK
PCI Express x8 add-on cards N/A
PCI Express x16 add-on cards N/A
PCI Express x32 add-on cards N/A
HTX add-on cards N/A
Legacy / Super I/O
Floppy N/A
Serial port 1 (COM1) N/A
Serial port 2 (COM2) N/A
Parallel port N/A
PS/2 keyboard N/A
PS/2 mouse N/A
Game port N/A
Infrared N/A
PC speaker N/A
DiskOnChip N/A
Input
Trackpoint N/A
Touchpad N/A
Fn Hotkeys N/A
Fingerprint Reader N/A
Laptop
Docking VGA N/A
Docking LAN N/A
Docking USB N/A
Docking Audio N/A
Docking Displayport N/A
Thinklight N/A
Webcam N/A
Miscellaneous
Sensors / fan control WIP
Hardware watchdog Untested
SMBus Unknown
CAN bus N/A
CPU frequency scaling OK
Other powersaving features OK
ACPI OK
Reboot OK
Poweroff OK
Suspend Unknown
Nonstandard LEDs N/A
High precision event timers (HPET) Need to test
Random number generator (RNG) N/A
Wake on modem ring N/A
Wake on LAN N/A
Wake on keyboard Fail
Wake on mouse Fail
Flashrom Unknown

OS Install

  • Win7 Ultimate x64 SP1
    • Setup from DVD: OK
    • Install latest graphics driver: OK
  • Ubuntu 13.10
    • Setup from DVD: OK
    • Install latest graphics driver: OK

Bootlog

coreboot-4.0-6958-gea8f3b4 Thu Sep 25 11:07:51 CST 2014 starting...
BSP Family_Model: 00730f00 
cpu_init_detectedx = 00000000 
agesawrapper_amdinitreset() entry

Fch OEM config in INIT RESET
Done
agesawrapper_amdinitearly() returned AGESA_SUCCESS
agesawrapper_amdinitpost() entry
-------------READING SPD-----------
iobase: 0x00000B00, SmbusSlave: 0x000000A0, count: 128
-------------SPD READ ERROR-----------
-------------READING SPD-----------
iobase: 0x00000B00, SmbusSlave: 0x000000A2, count: 128

-------------FINISHED READING SPD-----------
setup_uma_memory: syslimit 0x11EFF0000, bottomio 0x00e00000
setup_uma_memory: uma size 512MB, uma start 0xc0000000
agesawrapper_amdinitpost() returned AGESA_SUCCESS
agesawrapper_amdinitenv() entry
Fch OEM config in INIT ENV Done
agesawrapper_amdinitenv() returned AGESA_SUCCESS
Trying CBFS ramstage loader.
CBFS: loading stage fallback/ramstage @ 0x200000 (995372 bytes), entry @ 0x200000
coreboot-4.0-6958-gea8f3b4 Thu Sep 25 11:07:51 CST 2014 booting...
BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:02.1: enabled 1
PCI: 00:02.2: enabled 1
PCI: 00:02.3: enabled 1
PCI: 00:02.4: enabled 1
PCI: 00:02.5: enabled 1
PCI: 00:10.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PCI: 00:14.7: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
Compare with tree...
Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:01.1: enabled 1
  PCI: 00:02.0: enabled 1
  PCI: 00:02.1: enabled 1
  PCI: 00:02.2: enabled 1
  PCI: 00:02.3: enabled 1
  PCI: 00:02.4: enabled 1
  PCI: 00:02.5: enabled 1
  PCI: 00:10.0: enabled 1
  PCI: 00:11.0: enabled 1
  PCI: 00:12.0: enabled 1
  PCI: 00:12.2: enabled 1
  PCI: 00:13.0: enabled 1
  PCI: 00:13.2: enabled 1
  PCI: 00:14.0: enabled 1
   I2C: 00:50: enabled 1
   I2C: 00:51: enabled 1
  PCI: 00:14.2: enabled 1
  PCI: 00:14.3: enabled 1
  PCI: 00:14.7: enabled 1
  PCI: 00:18.0: enabled 1
  PCI: 00:18.1: enabled 1
  PCI: 00:18.2: enabled 1
  PCI: 00:18.3: enabled 1
  PCI: 00:18.4: enabled 1
  PCI: 00:18.5: enabled 1
Mainboard DB-FT3b Enable.
scan_static_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi = 0x00000001
setup_uma_memory: system memory size 4GB, topmem2 size 4592MB, topmem size 3584MB
setup_uma_memory: uma size 0x20000000, memory start 0xc0000000
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
MullinsPI Debug: Grabbing the AMD Topology Information.
MullinsPI Debug: AMD Topology Number of Modules (@0x00232ed4) is 1
MullinsPI Debug: AMD Topology Number of IOAPICs (@0xffe5f1c8) is 3
PCI: 00:18.5 family16h, core_max=0x8, core_nums=0x7, siblings=0x3
node 0x0 core 0x0 apicid=0x0
CPU: APIC: 00 enabled
node 0x0 core 0x1 apicid=0x1
CPU: APIC: 01 enabled
node 0x0 core 0x2 apicid=0x2
CPU: APIC: 02 enabled
node 0x0 core 0x3 apicid=0x3
CPU: APIC: 03 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1022/1566] ops
PCI: 00:00.0 [1022/1566] enabled
PCI: 00:01.0 [1002/9855] enabled
PCI: 00:01.1 [1002/9840] enabled
PCI: 00:02.0 [1022/156b] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:02.1 subordinate bus PCI Express
PCI: 00:02.1 [1022/1439] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:02.2 subordinate bus PCI Express
PCI: 00:02.2 [1022/1439] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:02.3 subordinate bus PCI Express
PCI: 00:02.3 [1022/1439] enabled
PCI: Static device PCI: 00:02.4 not found, disabling it.
PCI: Static device PCI: 00:02.5 not found, disabling it.
PCI: 00:08.0 [1022/1537] enabled
hudson_enable()
PCI: 00:10.0 [1022/7814] enabled
hudson_enable()
PCI: 00:11.0 [1022/7800] ops
PCI: 00:11.0 [1022/7800] enabled
hudson_enable()
PCI: 00:12.0 [1022/7808] ops
PCI: 00:12.0 [1022/7808] enabled
hudson_enable()
PCI: 00:13.0 [1022/7808] ops
PCI: 00:13.0 [1022/7808] enabled
hudson_enable()
PCI: 00:14.0 [1022/780b] bus ops
PCI: 00:14.0 [1022/780b] enabled
hudson_enable()
PCI: 00:14.2 [1022/780d] ops
PCI: 00:14.2 [1022/780d] enabled
hudson_enable()
PCI: 00:14.3 [1022/780e] bus ops
PCI: 00:14.3 [1022/780e] enabled
hudson_enable()
PCI: 00:14.7 [1022/7813] ops
PCI: 00:14.7 [1022/7813] enabled
PCI: 00:18.0 [1022/1580] enabled
PCI: 00:18.1 [1022/1581] enabled
PCI: 00:18.2 [1022/1582] enabled
PCI: 00:18.3 [1022/1583] enabled
PCI: 00:18.4 [1022/1584] enabled
PCI: 00:18.5 [1022/1585] enabled
PCI: Left over static devices:
PCI: 00:12.2
PCI: 00:13.2
PCI: Check your devicetree.cb.
do_pci_scan_bridge for PCI: 00:02.1
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [8086/10d3] enabled
PCI: pci_scan_bus returning with max=001
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:02.2
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [14e4/4357] enabled
PCI: pci_scan_bus returning with max=002
Capability: type 0x01 @ 0x40
Capability: type 0x09 @ 0x58
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0xd0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:02.3
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [10ec/8168] enabled
PCI: 03:00.1 [10ec/816a] enabled
PCI: 03:00.2 [10ec/816b] enabled
PCI: 03:00.3 [10ec/816c] enabled
PCI: pci_scan_bus returning with max=003
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
do_pci_scan_bridge returns max 3
scan_static_bus for PCI: 00:14.0
smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
scan_static_bus for PCI: 00:14.0 done
scan_static_bus for PCI: 00:14.3
scan_static_bus for PCI: 00:14.3 done
PCI: pci_scan_bus returning with max=003
scan_static_bus for Root Device done
done
BS: BS_DEV_ENUMERATE times (us): entry 0 run 288165 exit 0
found VGA at PCI: 00:01.0
Setting up VGA for PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC: 02 missing read_resources
APIC: 03 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
fx_devs=0x1
DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:02.1 read_resources bus 1 link: 0
PCI: 00:02.1 read_resources bus 1 link: 0 done
PCI: 00:02.2 read_resources bus 2 link: 0
PCI: 00:02.2 read_resources bus 2 link: 0 done
PCI: 00:02.3 read_resources bus 3 link: 0
PCI: 00:02.3 read_resources bus 3 link: 0 done
PCI: 00:14.0 read_resources bus 1 link: 0
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
PCI: 00:14.0 read_resources bus 1 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI: 00:18.0 read_resources bus 0 link: 3
PCI: 00:18.0 read_resources bus 0 link: 3 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
  CPU_CLUSTER: 0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
   APIC: 00
   APIC: 01
   APIC: 02
   APIC: 03
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 10
   PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18
   PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20
   PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24
   PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
   PCI: 00:01.1
   PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:02.0
   PCI: 00:02.1 child on link 0 PCI: 01:00.0
   PCI: 00:02.1 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
   PCI: 00:02.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:02.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
    PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 14
    PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
    PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
    PCI: 01:00.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 2200 index 30
   PCI: 00:02.2 child on link 0 PCI: 02:00.0
   PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
   PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:02.3 child on link 0 PCI: 03:00.0
   PCI: 00:02.3 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
   PCI: 00:02.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:02.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 03:00.0
    PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
    PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
    PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
    PCI: 03:00.1
    PCI: 03:00.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
    PCI: 03:00.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
    PCI: 03:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
    PCI: 03:00.2
    PCI: 03:00.2 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
    PCI: 03:00.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
    PCI: 03:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
    PCI: 03:00.3
    PCI: 03:00.3 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
    PCI: 03:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 18
    PCI: 03:00.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
   PCI: 00:02.4
   PCI: 00:02.5
   PCI: 00:08.0
   PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10
   PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18
   PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
   PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20
   PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24
   PCI: 00:10.0
   PCI: 00:10.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
   PCI: 00:11.0
   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
   PCI: 00:12.0
   PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
   PCI: 00:13.0
   PCI: 00:13.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
   PCI: 00:14.0 child on link 0 I2C: 01:50
    I2C: 01:50
    I2C: 01:51
   PCI: 00:14.2
   PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.3
   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:14.7
   PCI: 00:14.7 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
   PCI: 00:18.0
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.4
   PCI: 00:18.5
DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:02.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 01:00.0 18 *  [0x0 - 0x1f] io
PCI: 00:02.1 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:02.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:02.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:02.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:00.0 10 *  [0x0 - 0xff] io
PCI: 03:00.1 10 *  [0x400 - 0x4ff] io
PCI: 03:00.2 10 *  [0x800 - 0x8ff] io
PCI: 03:00.3 10 *  [0xc00 - 0xcff] io
PCI: 00:02.3 compute_resources_io: base: d00 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:02.1 1c *  [0x0 - 0xfff] io
PCI: 00:02.3 1c *  [0x1000 - 0x1fff] io
PCI: 00:01.0 20 *  [0x2000 - 0x20ff] io
PCI: 00:11.0 20 *  [0x2400 - 0x240f] io
PCI: 00:11.0 10 *  [0x2410 - 0x2417] io
PCI: 00:11.0 18 *  [0x2418 - 0x241f] io
PCI: 00:11.0 14 *  [0x2420 - 0x2423] io
PCI: 00:11.0 1c *  [0x2424 - 0x2427] io
DOMAIN: 0000 compute_resources_io: base: 2428 size: 2428 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:02.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:02.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:02.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 14 *  [0x0 - 0x7ffff] mem
PCI: 01:00.0 30 *  [0x80000 - 0xbffff] mem
PCI: 01:00.0 10 *  [0xc0000 - 0xdffff] mem
PCI: 01:00.0 1c *  [0xe0000 - 0xe3fff] mem
PCI: 00:02.1 compute_resources_mem: base: e4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:02.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:02.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:02.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 10 *  [0x0 - 0x3fff] mem
PCI: 00:02.2 compute_resources_mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:02.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 03:00.0 20 *  [0x0 - 0x3fff] prefmem
PCI: 00:02.3 compute_resources_prefmem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:02.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.1 20 *  [0x0 - 0x3fff] mem
PCI: 03:00.2 20 *  [0x4000 - 0x7fff] mem
PCI: 03:00.3 20 *  [0x8000 - 0xbfff] mem
PCI: 03:00.0 18 *  [0xc000 - 0xcfff] mem
PCI: 03:00.1 18 *  [0xd000 - 0xdfff] mem
PCI: 03:00.2 18 *  [0xe000 - 0xefff] mem
PCI: 03:00.3 18 *  [0xf000 - 0xf0ff] mem
PCI: 00:02.3 compute_resources_mem: base: f100 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 10 *  [0x0 - 0xfffffff] prefmem
PCI: 00:01.0 18 *  [0x10000000 - 0x107fffff] prefmem
PCI: 00:02.1 20 *  [0x10800000 - 0x108fffff] mem
PCI: 00:02.2 20 *  [0x10900000 - 0x109fffff] mem
PCI: 00:02.3 24 *  [0x10a00000 - 0x10afffff] prefmem
PCI: 00:02.3 20 *  [0x10b00000 - 0x10bfffff] mem
PCI: 00:08.0 18 *  [0x10c00000 - 0x10cfffff] mem
PCI: 00:08.0 20 *  [0x10d00000 - 0x10dfffff] mem
PCI: 00:01.0 24 *  [0x10e00000 - 0x10e3ffff] mem
PCI: 00:01.0 30 *  [0x10e40000 - 0x10e5ffff] mem
PCI: 00:08.0 10 *  [0x10e60000 - 0x10e7ffff] prefmem
PCI: 00:01.1 10 *  [0x10e80000 - 0x10e83fff] mem
PCI: 00:14.2 10 *  [0x10e84000 - 0x10e87fff] mem
PCI: 00:08.0 24 *  [0x10e88000 - 0x10e89fff] mem
PCI: 00:10.0 10 *  [0x10e8a000 - 0x10e8bfff] mem
PCI: 00:08.0 1c *  [0x10e8c000 - 0x10e8cfff] mem
PCI: 00:11.0 24 *  [0x10e8d000 - 0x10e8d3ff] mem
PCI: 00:12.0 10 *  [0x10e8d400 - 0x10e8d4ff] mem
PCI: 00:13.0 10 *  [0x10e8d500 - 0x10e8d5ff] mem
PCI: 00:14.7 10 *  [0x10e8d600 - 0x10e8d6ff] mem
DOMAIN: 0000 compute_resources_mem: base: 10e8d700 size: 10e8d700 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:01.1
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:02.1
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:02.2
constrain_resources: PCI: 02:00.0
constrain_resources: PCI: 00:02.3
constrain_resources: PCI: 03:00.0
constrain_resources: PCI: 03:00.1
constrain_resources: PCI: 03:00.2
constrain_resources: PCI: 03:00.3
constrain_resources: PCI: 00:08.0
constrain_resources: PCI: 00:10.0
constrain_resources: PCI: 00:11.0
constrain_resources: PCI: 00:12.0
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:14.0
constrain_resources: I2C: 01:50
constrain_resources: I2C: 01:51
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PCI: 00:14.7
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
constrain_resources: PCI: 00:18.5
avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
	lim->base 00000000 lim->limit febfffff
Setting resources...
DOMAIN: 0000 allocate_resources_io: base:1000 size:2428 align:12 gran:0 limit:ffff
Assigned: PCI: 00:02.1 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:02.3 1c *  [0x2000 - 0x2fff] io
Assigned: PCI: 00:01.0 20 *  [0x3000 - 0x30ff] io
Assigned: PCI: 00:11.0 20 *  [0x3400 - 0x340f] io
Assigned: PCI: 00:11.0 10 *  [0x3410 - 0x3417] io
Assigned: PCI: 00:11.0 18 *  [0x3418 - 0x341f] io
Assigned: PCI: 00:11.0 14 *  [0x3420 - 0x3423] io
Assigned: PCI: 00:11.0 1c *  [0x3424 - 0x3427] io
DOMAIN: 0000 allocate_resources_io: next_base: 3428 size: 2428 align: 12 gran: 0 done
PCI: 00:02.1 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:00.0 18 *  [0x1000 - 0x101f] io
PCI: 00:02.1 allocate_resources_io: next_base: 1020 size: 1000 align: 12 gran: 12 done
PCI: 00:02.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:02.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:02.3 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 03:00.0 10 *  [0x2000 - 0x20ff] io
Assigned: PCI: 03:00.1 10 *  [0x2400 - 0x24ff] io
Assigned: PCI: 03:00.2 10 *  [0x2800 - 0x28ff] io
Assigned: PCI: 03:00.3 10 *  [0x2c00 - 0x2cff] io
PCI: 00:02.3 allocate_resources_io: next_base: 2d00 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10e8d700 align:28 gran:0 limit:febfffff
Assigned: PCI: 00:01.0 10 *  [0xe0000000 - 0xefffffff] prefmem
Assigned: PCI: 00:01.0 18 *  [0xf0000000 - 0xf07fffff] prefmem
Assigned: PCI: 00:02.1 20 *  [0xf0800000 - 0xf08fffff] mem
Assigned: PCI: 00:02.2 20 *  [0xf0900000 - 0xf09fffff] mem
Assigned: PCI: 00:02.3 24 *  [0xf0a00000 - 0xf0afffff] prefmem
Assigned: PCI: 00:02.3 20 *  [0xf0b00000 - 0xf0bfffff] mem
Assigned: PCI: 00:08.0 18 *  [0xf0c00000 - 0xf0cfffff] mem
Assigned: PCI: 00:08.0 20 *  [0xf0d00000 - 0xf0dfffff] mem
Assigned: PCI: 00:01.0 24 *  [0xf0e00000 - 0xf0e3ffff] mem
Assigned: PCI: 00:01.0 30 *  [0xf0e40000 - 0xf0e5ffff] mem
Assigned: PCI: 00:08.0 10 *  [0xf0e60000 - 0xf0e7ffff] prefmem
Assigned: PCI: 00:01.1 10 *  [0xf0e80000 - 0xf0e83fff] mem
Assigned: PCI: 00:14.2 10 *  [0xf0e84000 - 0xf0e87fff] mem
Assigned: PCI: 00:08.0 24 *  [0xf0e88000 - 0xf0e89fff] mem
Assigned: PCI: 00:10.0 10 *  [0xf0e8a000 - 0xf0e8bfff] mem
Assigned: PCI: 00:08.0 1c *  [0xf0e8c000 - 0xf0e8cfff] mem
Assigned: PCI: 00:11.0 24 *  [0xf0e8d000 - 0xf0e8d3ff] mem
Assigned: PCI: 00:12.0 10 *  [0xf0e8d400 - 0xf0e8d4ff] mem
Assigned: PCI: 00:13.0 10 *  [0xf0e8d500 - 0xf0e8d5ff] mem
Assigned: PCI: 00:14.7 10 *  [0xf0e8d600 - 0xf0e8d6ff] mem
DOMAIN: 0000 allocate_resources_mem: next_base: f0e8d700 size: 10e8d700 align: 28 gran: 0 done
PCI: 00:02.1 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:02.1 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:02.1 allocate_resources_mem: base:f0800000 size:100000 align:20 gran:20 limit:febfffff
Assigned: PCI: 01:00.0 14 *  [0xf0800000 - 0xf087ffff] mem
Assigned: PCI: 01:00.0 30 *  [0xf0880000 - 0xf08bffff] mem
Assigned: PCI: 01:00.0 10 *  [0xf08c0000 - 0xf08dffff] mem
Assigned: PCI: 01:00.0 1c *  [0xf08e0000 - 0xf08e3fff] mem
PCI: 00:02.1 allocate_resources_mem: next_base: f08e4000 size: 100000 align: 20 gran: 20 done
PCI: 00:02.2 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:02.2 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:02.2 allocate_resources_mem: base:f0900000 size:100000 align:20 gran:20 limit:febfffff
Assigned: PCI: 02:00.0 10 *  [0xf0900000 - 0xf0903fff] mem
PCI: 00:02.2 allocate_resources_mem: next_base: f0904000 size: 100000 align: 20 gran: 20 done
PCI: 00:02.3 allocate_resources_prefmem: base:f0a00000 size:100000 align:20 gran:20 limit:febfffff
Assigned: PCI: 03:00.0 20 *  [0xf0a00000 - 0xf0a03fff] prefmem
PCI: 00:02.3 allocate_resources_prefmem: next_base: f0a04000 size: 100000 align: 20 gran: 20 done
PCI: 00:02.3 allocate_resources_mem: base:f0b00000 size:100000 align:20 gran:20 limit:febfffff
Assigned: PCI: 03:00.1 20 *  [0xf0b00000 - 0xf0b03fff] mem
Assigned: PCI: 03:00.2 20 *  [0xf0b04000 - 0xf0b07fff] mem
Assigned: PCI: 03:00.3 20 *  [0xf0b08000 - 0xf0b0bfff] mem
Assigned: PCI: 03:00.0 18 *  [0xf0b0c000 - 0xf0b0cfff] mem
Assigned: PCI: 03:00.1 18 *  [0xf0b0d000 - 0xf0b0dfff] mem
Assigned: PCI: 03:00.2 18 *  [0xf0b0e000 - 0xf0b0efff] mem
Assigned: PCI: 03:00.3 18 *  [0xf0b0f000 - 0xf0b0f0ff] mem
PCI: 00:02.3 allocate_resources_mem: next_base: f0b0f100 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
CPU_CLUSTER: 0 c0010058 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x00 mem <mmconfig>
CPU_CLUSTER: 0 assign_resources, bus 0 link: 0
CPU_CLUSTER: 0 assign_resources, bus 0 link: 0
node 0: mmio_basek=00380000, basek=00400000, limitk=00460000
CBMEM region bffe0000-bfffffff (cbmem_late_set_table)
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:01.0 18 <- [0x00f0000000 - 0x00f07fffff] size 0x00800000 gran 0x17 prefmem64
PCI: 00:01.0 20 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io
PCI: 00:01.0 24 <- [0x00f0e00000 - 0x00f0e3ffff] size 0x00040000 gran 0x12 mem
PCI: 00:01.0 30 <- [0x00f0e40000 - 0x00f0e5ffff] size 0x00020000 gran 0x11 romem
PCI: 00:01.1 10 <- [0x00f0e80000 - 0x00f0e83fff] size 0x00004000 gran 0x0e mem64
PCI: 00:02.1 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:02.1 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:02.1 20 <- [0x00f0800000 - 0x00f08fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:02.1 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00f08c0000 - 0x00f08dffff] size 0x00020000 gran 0x11 mem
PCI: 01:00.0 14 <- [0x00f0800000 - 0x00f087ffff] size 0x00080000 gran 0x13 mem
PCI: 01:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
PCI: 01:00.0 1c <- [0x00f08e0000 - 0x00f08e3fff] size 0x00004000 gran 0x0e mem
PCI: 01:00.0 30 <- [0x00f0880000 - 0x00f08bffff] size 0x00040000 gran 0x12 romem
PCI: 00:02.1 assign_resources, bus 1 link: 0
PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:02.2 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:02.2 20 <- [0x00f0900000 - 0x00f09fffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:02.2 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x00f0900000 - 0x00f0903fff] size 0x00004000 gran 0x0e mem64
PCI: 00:02.2 assign_resources, bus 2 link: 0
PCI: 00:02.3 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:02.3 24 <- [0x00f0a00000 - 0x00f0afffff] size 0x00100000 gran 0x14 bus 03 prefmem
PCI: 00:02.3 20 <- [0x00f0b00000 - 0x00f0bfffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:02.3 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 03:00.0 18 <- [0x00f0b0c000 - 0x00f0b0cfff] size 0x00001000 gran 0x0c mem64
PCI: 03:00.0 20 <- [0x00f0a00000 - 0x00f0a03fff] size 0x00004000 gran 0x0e prefmem64
PCI: 03:00.1 10 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io
PCI: 03:00.1 18 <- [0x00f0b0d000 - 0x00f0b0dfff] size 0x00001000 gran 0x0c mem64
PCI: 03:00.1 20 <- [0x00f0b00000 - 0x00f0b03fff] size 0x00004000 gran 0x0e mem64
PCI: 03:00.2 10 <- [0x0000002800 - 0x00000028ff] size 0x00000100 gran 0x08 io
PCI: 03:00.2 18 <- [0x00f0b0e000 - 0x00f0b0efff] size 0x00001000 gran 0x0c mem64
PCI: 03:00.2 20 <- [0x00f0b04000 - 0x00f0b07fff] size 0x00004000 gran 0x0e mem64
PCI: 03:00.3 10 <- [0x0000002c00 - 0x0000002cff] size 0x00000100 gran 0x08 io
PCI: 03:00.3 18 <- [0x00f0b0f000 - 0x00f0b0f0ff] size 0x00000100 gran 0x08 mem64
PCI: 03:00.3 20 <- [0x00f0b08000 - 0x00f0b0bfff] size 0x00004000 gran 0x0e mem64
PCI: 00:02.3 assign_resources, bus 3 link: 0
PCI: 00:08.0 10 <- [0x00f0e60000 - 0x00f0e7ffff] size 0x00020000 gran 0x11 prefmem64
PCI: 00:08.0 18 <- [0x00f0c00000 - 0x00f0cfffff] size 0x00100000 gran 0x14 mem
PCI: 00:08.0 1c <- [0x00f0e8c000 - 0x00f0e8cfff] size 0x00001000 gran 0x0c mem
PCI: 00:08.0 20 <- [0x00f0d00000 - 0x00f0dfffff] size 0x00100000 gran 0x14 mem
PCI: 00:08.0 24 <- [0x00f0e88000 - 0x00f0e89fff] size 0x00002000 gran 0x0d mem
PCI: 00:10.0 10 <- [0x00f0e8a000 - 0x00f0e8bfff] size 0x00002000 gran 0x0d mem64
PCI: 00:11.0 10 <- [0x0000003410 - 0x0000003417] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000003420 - 0x0000003423] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000003418 - 0x000000341f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000003424 - 0x0000003427] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000003400 - 0x000000340f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00f0e8d000 - 0x00f0e8d3ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00f0e8d400 - 0x00f0e8d4ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00f0e8d500 - 0x00f0e8d5ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.2 10 <- [0x00f0e84000 - 0x00f0e87fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.7 10 <- [0x00f0e8d600 - 0x00f0e8d6ff] size 0x00000100 gran 0x08 mem64
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
  CPU_CLUSTER: 0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
   APIC: 00
   APIC: 01
   APIC: 02
   APIC: 03
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 1000 size 2428 align 12 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base e0000000 size 10e8d700 align 28 gran 0 limit febfffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
  DOMAIN: 0000 resource base c0000 size dff40000 align 0 gran 0 limit 0 flags e0004200 index 20
  DOMAIN: 0000 resource base 100000000 size 1f000000 align 0 gran 0 limit 0 flags e0004200 index 30
  DOMAIN: 0000 resource base c0000000 size 20000000 align 0 gran 0 limit 0 flags f0000200 index 7
   PCI: 00:00.0
   PCI: 00:01.0
   PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001201 index 10
   PCI: 00:01.0 resource base f0000000 size 800000 align 23 gran 23 limit febfffff flags 60001201 index 18
   PCI: 00:01.0 resource base 3000 size 100 align 8 gran 8 limit ffff flags 60000100 index 20
   PCI: 00:01.0 resource base f0e00000 size 40000 align 18 gran 18 limit febfffff flags 60000200 index 24
   PCI: 00:01.0 resource base f0e40000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30
   PCI: 00:01.1
   PCI: 00:01.1 resource base f0e80000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10
   PCI: 00:02.0
   PCI: 00:02.1 child on link 0 PCI: 01:00.0
   PCI: 00:02.1 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:02.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
   PCI: 00:02.1 resource base f0800000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base f08c0000 size 20000 align 17 gran 17 limit febfffff flags 60000200 index 10
    PCI: 01:00.0 resource base f0800000 size 80000 align 19 gran 19 limit febfffff flags 60000200 index 14
    PCI: 01:00.0 resource base 1000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18
    PCI: 01:00.0 resource base f08e0000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 1c
    PCI: 01:00.0 resource base f0880000 size 40000 align 18 gran 18 limit febfffff flags 60002200 index 30
   PCI: 00:02.2 child on link 0 PCI: 02:00.0
   PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:02.2 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
   PCI: 00:02.2 resource base f0900000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base f0900000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10
   PCI: 00:02.3 child on link 0 PCI: 03:00.0
   PCI: 00:02.3 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:02.3 resource base f0a00000 size 100000 align 20 gran 20 limit febfffff flags 60081202 index 24
   PCI: 00:02.3 resource base f0b00000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20
    PCI: 03:00.0
    PCI: 03:00.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
    PCI: 03:00.0 resource base f0b0c000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 18
    PCI: 03:00.0 resource base f0a00000 size 4000 align 14 gran 14 limit febfffff flags 60001201 index 20
    PCI: 03:00.1
    PCI: 03:00.1 resource base 2400 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
    PCI: 03:00.1 resource base f0b0d000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 18
    PCI: 03:00.1 resource base f0b00000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 20
    PCI: 03:00.2
    PCI: 03:00.2 resource base 2800 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
    PCI: 03:00.2 resource base f0b0e000 size 1000 align 12 gran 12 limit febfffff flags 60000201 index 18
    PCI: 03:00.2 resource base f0b04000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 20
    PCI: 03:00.3
    PCI: 03:00.3 resource base 2c00 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
    PCI: 03:00.3 resource base f0b0f000 size 100 align 8 gran 8 limit febfffff flags 60000201 index 18
    PCI: 03:00.3 resource base f0b08000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 20
   PCI: 00:02.4
   PCI: 00:02.5
   PCI: 00:08.0
   PCI: 00:08.0 resource base f0e60000 size 20000 align 17 gran 17 limit febfffff flags 60001201 index 10
   PCI: 00:08.0 resource base f0c00000 size 100000 align 20 gran 20 limit febfffff flags 60000200 index 18
   PCI: 00:08.0 resource base f0e8c000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 1c
   PCI: 00:08.0 resource base f0d00000 size 100000 align 20 gran 20 limit febfffff flags 60000200 index 20
   PCI: 00:08.0 resource base f0e88000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 24
   PCI: 00:10.0
   PCI: 00:10.0 resource base f0e8a000 size 2000 align 13 gran 13 limit febfffff flags 60000201 index 10
   PCI: 00:11.0
   PCI: 00:11.0 resource base 3410 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
   PCI: 00:11.0 resource base 3420 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
   PCI: 00:11.0 resource base 3418 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
   PCI: 00:11.0 resource base 3424 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
   PCI: 00:11.0 resource base 3400 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
   PCI: 00:11.0 resource base f0e8d000 size 400 align 10 gran 10 limit febfffff flags 60000200 index 24
   PCI: 00:12.0
   PCI: 00:12.0 resource base f0e8d400 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10
   PCI: 00:13.0
   PCI: 00:13.0 resource base f0e8d500 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10
   PCI: 00:14.0 child on link 0 I2C: 01:50
    I2C: 01:50
    I2C: 01:51
   PCI: 00:14.2
   PCI: 00:14.2 resource base f0e84000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10
   PCI: 00:14.3
   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:14.7
   PCI: 00:14.7 resource base f0e8d600 size 100 align 8 gran 8 limit febfffff flags 60000201 index 10
   PCI: 00:18.0
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.4
   PCI: 00:18.5
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 1302228 exit 0
Warning: Can't write PCI_INTR 0xC00/0xC01 registers because
'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL
Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist
Enabling resources...
agesawrapper_amdinitmid() entry
agesawrapper_amdinitmid() returned AGESA_SUCCESS
  ader - leaving domain_enable_resources.
PCI: 00:00.0 cmd <- 04
PCI: 00:01.0 subsystem <- 1022/1410
PCI: 00:01.0 cmd <- 07
PCI: 00:01.1 subsystem <- 1022/1410
PCI: 00:01.1 cmd <- 02
PCI: 00:02.0 subsystem <- 1022/1410
PCI: 00:02.0 cmd <- 00
PCI: 00:02.1 bridge ctrl <- 0003
PCI: 00:02.1 cmd <- 07
PCI: 00:02.2 bridge ctrl <- 0003
PCI: 00:02.2 cmd <- 06
PCI: 00:02.3 bridge ctrl <- 0003
PCI: 00:02.3 cmd <- 07
PCI: 00:08.0 cmd <- 06
PCI: 00:10.0 subsystem <- 1022/1410
PCI: 00:10.0 cmd <- 02
PCI: 00:11.0 cmd <- 07
PCI: 00:12.0 subsystem <- 1022/1410
PCI: 00:12.0 cmd <- 02
PCI: 00:13.0 subsystem <- 1022/1410
PCI: 00:13.0 cmd <- 02
PCI: 00:14.0 subsystem <- 1022/1410
PCI: 00:14.0 cmd <- 403
PCI: 00:14.2 subsystem <- 1022/1410
PCI: 00:14.2 cmd <- ffff
PCI: 00:14.3 subsystem <- 1022/1410
PCI: 00:14.3 cmd <- 0f
PCI: 00:14.7 cmd <- 06
PCI: 00:18.0 subsystem <- 1022/1410
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1022/1410
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/1410
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 subsystem <- 1022/1410
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 subsystem <- 1022/1410
PCI: 00:18.4 cmd <- 00
PCI: 00:18.5 subsystem <- 1022/1410
PCI: 00:18.5 cmd <- 00
PCI: 01:00.0 cmd <- 03
PCI: 02:00.0 cmd <- 02
PCI: 03:00.0 cmd <- 03
PCI: 03:00.1 cmd <- 03
PCI: 03:00.2 cmd <- 03
PCI: 03:00.3 cmd <- 03
done.
BS: BS_DEV_ENABLE times (us): entry 9625 run 1124583 exit 0
Initializing devices...
Root Device init
Root Device init 825 usecs
CPU_CLUSTER: 0 init
start_eip=0x00001000, code_size=0x00000031
Initializing CPU #0
CPU: vendor AMD device 730f00
CPU: family 16, model 30, stepping 00
Model 16 Init.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Enabling cache
Setting up local apic... apic_id: 0x00 done.
siblings = 03, CPU #0 initialized
CPU1: stack_base 00231000, stack_end 00231ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
CPU: vendor AMD device 730f00
CPU: family 16, model 30, stepping 00
Model 16 Init.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Enabling cache
Setting up local apic... apic_id: 0x01 done.
siblings = 03, CPU #1 initialized
CPU2: stack_base 00230000, stack_end 00230ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 2.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 2.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #2
CPU: vendor AMD device 730f00
CPU: family 16, model 30, stepping 00
Model 16 Init.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Enabling cache
Setting up local apic... apic_id: 0x02 done.
siblings = 03, CPU #2 initialized
CPU3: stack_base 0022f000, stack_end 0022fff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 3.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 3.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #3
Waiting for 1 CPUS to stop
CPU: vendor AMD device 730f00
CPU: family 16, model 30, stepping 00
Model 16 Init.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Enabling cache
Setting up local apic... apic_id: 0x03 done.
siblings = 03, CPU #3 initialized
All AP CPUs stopped (1085 loops)
CPU1: stack: 00231000 - 00232000, lowest used address 00231dc8, stack used: 568 bytes
CPU2: stack: 00230000 - 00231000, lowest used address 00230dc8, stack used: 568 bytes
CPU3: stack: 0022f000 - 00230000, lowest used address 0022fdc8, stack used: 568 bytes
CPU_CLUSTER: 0 init 147421 usecs
PCI: 00:00.0 init
PCI: 00:00.0 init 827 usecs
PCI: 00:01.0 init
Mapping PCI device 10029855 to 10029850
In CBFS, ROM address for PCI: 00:01.0 = ff800778
PCI expansion ROM, signature 0xaa55, INIT size 0xec00, data ptr 0x01c4
PCI ROM image, vendor ID 1002, device ID 9850,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from ff800778 to 0xc0000, 0xec00 bytes
Real mode stub @00000600: 867 bytes
Calling Option ROM...
... Option ROM returned.
VGA Option ROM was run
PCI: 00:01.0 init 47267 usecs
PCI: 00:01.1 init
PCI: 00:01.1 init 827 usecs
PCI: 00:02.0 init
PCI: 00:02.0 init 826 usecs
PCI: 00:08.0 init
PCI: 00:08.0 init 826 usecs
PCI: 00:10.0 init
PCI: 00:10.0 init 826 usecs
PCI: 00:11.0 init
PCI: 00:11.0 init 826 usecs
PCI: 00:12.0 init
PCI: 00:12.0 init 827 usecs
PCI: 00:13.0 init
PCI: 00:13.0 init 826 usecs
PCI: 00:14.0 init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x04
IOAPIC: Dumping registers
  reg 0x0000: 0x04000000
  reg 0x0001: 0x00178021
  reg 0x0002: 0x04000000
IOAPIC: 24 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
PCI: 00:14.0 init 66845 usecs
PCI: 00:14.2 init
PCI: 00:14.2 init 827 usecs
PCI: 00:14.3 init
RTC Init
PCI: 00:14.3 init 1281 usecs
PCI: 00:14.7 init
PCI: 00:14.7 init 828 usecs
PCI: 00:18.0 init
PCI: 00:18.0 init 827 usecs
PCI: 00:18.1 init
PCI: 00:18.1 init 826 usecs
PCI: 00:18.2 init
PCI: 00:18.2 init 826 usecs
PCI: 00:18.3 init
PCI: 00:18.3 init 826 usecs
PCI: 00:18.4 init
PCI: 00:18.4 init 826 usecs
PCI: 00:18.5 init
PCI: 00:18.5 init 827 usecs
PCI: 01:00.0 init
PCI: 01:00.0 init 826 usecs
PCI: 02:00.0 init
PCI: 02:00.0 init 826 usecs
PCI: 03:00.0 init
PCI: 03:00.0 init 826 usecs
PCI: 03:00.1 init
PCI: 03:00.1 init 826 usecs
PCI: 03:00.2 init
PCI: 03:00.2 init 826 usecs
PCI: 03:00.3 init
PCI: 03:00.3 init 826 usecs
Devices initialized
Show all devs...After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:02.1: enabled 1
PCI: 00:02.2: enabled 1
PCI: 00:02.3: enabled 1
PCI: 00:02.4: enabled 0
PCI: 00:02.5: enabled 0
PCI: 00:10.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 01:50: enabled 1
I2C: 01:51: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PCI: 00:14.7: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
APIC: 01: enabled 1
APIC: 02: enabled 1
APIC: 03: enabled 1
PCI: 00:08.0: enabled 1
PCI: 01:00.0: enabled 1
PCI: 02:00.0: enabled 1
PCI: 03:00.0: enabled 1
PCI: 03:00.1: enabled 1
PCI: 03:00.2: enabled 1
PCI: 03:00.3: enabled 1
BS: BS_DEV_INIT times (us): entry 0 run 363447 exit 0
CBMEM region bffe0000-bfffffff (cbmem_check_toc)
CBMEM region bffe0000-bfffffff (cbmem_initialize_empty)
Adding CBMEM entry as no. 1
Moving GDT to bffe0200...ok
Finalize devices...
Devices finalized
agesawrapper_amdinitlate() entry

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00a, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00a, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00a, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00a, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00a, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00a, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00a, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00a, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00a, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = 1180000, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = 1080000, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = 1040000, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a008, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00f, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a00e, Param2 = 0.
  Param3 = 0, Param4 = 0.

EventLog:  EventClass = 2, EventInfo = 8040100.
  Param1 = a010, Param2 = 0.
  Param3 = 0, Param4 = 0.
ASSERTION FAILED: file 'src/mainboard/amd/olivehillplus/agesawrapper.c',  line 369
DmiTable:1001129f, AcpiPstatein: 1001011b, AcpiSrat:0,AcpiSlit:0, Mce:10011123, Cmc:100111e5,Alib:10012431, AcpiIvrs:0 in agesawra
pper_amdinitlate
agesawrapper_amdinitlate() returned AGESA_ERROR
BS: BS_POST_DEVICE times (us): entry 7167 run 1741 exit 101044
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0xbffe0400...write_pirq_routing_table done.
PIRQ table: 48 bytes.
Wrote the mp table end at: 000f0410 - 000f05cc
Adding CBMEM entry as no. 3
Wrote the mp table end at: bffe1410 - bffe15cc
MP table: 460 bytes.
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at bffe2400...
ACPI:    * DSDT at bffe24c8
ACPI:    * DSDT @ bffe24c8 Length 167a
ACPI: * FACS at bffe3b48
ACPI:  * FADT at bffe3b88
pm_base: 0x0800
ACPI: added table 1/32, length now 40
ACPI:  * HPET at bffe3c80
ACPI: added table 2/32, length now 44
ACPI:  * MADT at bffe3cb8
ACPI: added table 3/32, length now 48
ACPI: added table 4/32, length now 52
ACPI:    * IVRS at bffe3f08
  AGESA IVRS table NULL. Skipping.
ACPI:    * SRAT at bffe3f08
  AGESA SRAT table NULL. Skipping.
ACPI:   * SLIT at bffe3f08
  AGESA SLIT table NULL. Skipping.
ACPI:  * AGESA ALIB SSDT at bffe3f10
ACPI: added table 5/32, length now 56
ACPI:    * SSDT at bffe8790
ACPI: added table 6/32, length now 60
ACPI:    * SSDT for PState at bffe8db4
ACPI:    * SSDT
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 27129 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: bffed800
Root Device (AMD DB-FT3b)
CPU_CLUSTER: 0 (AMD FAM16 Root Complex)
APIC: 00 (AMD CPU Family 16h)
DOMAIN: 0000 (AMD FAM16 Root Complex)
PCI: 00:00.0 (AMD FAM16 Northbridge)
PCI: 00:01.0 (AMD FAM16 Northbridge)
PCI: 00:01.1 (AMD FAM16 Northbridge)
PCI: 00:02.0 (AMD FAM16 Northbridge)
PCI: 00:02.1 (AMD FAM16 Northbridge)
PCI: 00:02.2 (AMD FAM16 Northbridge)
PCI: 00:02.3 (AMD FAM16 Northbridge)
PCI: 00:02.4 (AMD FAM16 Northbridge)
PCI: 00:02.5 (AMD FAM16 Northbridge)
PCI: 00:10.0 (ATI HUDSON)
PCI: 00:11.0 (ATI HUDSON)
PCI: 00:12.0 (ATI HUDSON)
PCI: 00:12.2 (ATI HUDSON)
PCI: 00:13.0 (ATI HUDSON)
PCI: 00:13.2 (ATI HUDSON)
PCI: 00:14.0 (ATI HUDSON)
I2C: 01:50 (unknown)
I2C: 01:51 (unknown)
PCI: 00:14.2 (ATI HUDSON)
PCI: 00:14.3 (ATI HUDSON)
PCI: 00:14.7 (ATI HUDSON)
PCI: 00:18.0 (AMD FAM16 Northbridge)
PCI: 00:18.1 (AMD FAM16 Northbridge)
PCI: 00:18.2 (AMD FAM16 Northbridge)
PCI: 00:18.3 (AMD FAM16 Northbridge)
PCI: 00:18.4 (AMD FAM16 Northbridge)
PCI: 00:18.5 (AMD FAM16 Northbridge)
APIC: 01 (unknown)
APIC: 02 (unknown)
APIC: 03 (unknown)
PCI: 00:08.0 (unknown)
PCI: 01:00.0 (unknown)
PCI: 02:00.0 (unknown)
PCI: 03:00.0 (unknown)
PCI: 03:00.1 (unknown)
PCI: 03:00.2 (unknown)
PCI: 03:00.3 (unknown)
SMBIOS tables: 333 bytes.
Adding CBMEM entry as no. 6
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5fdf
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0xbffee000
rom_table_end = 0xbffee000
... aligned to 0xbfff0000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-00000000bffdffff: RAM
 3. 00000000bffe0000-00000000bfffffff: CONFIGURATION TABLES
 4. 00000000c0000000-00000000dfffffff: RESERVED
 5. 00000000f8000000-00000000fbffffff: RESERVED
 6. 0000000100000000-000000011effffff: RAM
Wrote coreboot table at: bffee000, 0x164 bytes, checksum c3d4
coreboot table: 380 bytes.
FREE SPACE  0. bfff6000 0000a000
GDT         1. bffe0200 00000200
IRQ TABLE   2. bffe0400 00001000
SMP TABLE   3. bffe1400 00001000
ACPI        4. bffe2400 0000b400
SMBIOS      5. bffed800 00000800
COREBOOT    6. bffee000 00008000
BS: BS_WRITE_TABLES times (us): entry 0 run 154778 exit 0
CBFS: located payload @ ff83e8f8, 56173 bytes.
Loading segment from rom address 0xff83e8f8
  code (compression=1)
  New segment dstaddr 0xe5c18 memsize 0x1a3e8 srcaddr 0xff83e930 filesize 0xdb35
  (cleaned up) New segment addr 0xe5c18 size 0x1a3e8 offset 0xff83e930 filesize 0xdb35
Loading segment from rom address 0xff83e914
  Entry Point 0x000fd58c
Bounce Buffer at bfdf9000, 1990744 bytes
Loading Segment: addr: 0x00000000000e5c18 memsz: 0x000000000001a3e8 filesz: 0x000000000000db35
lb: [0x0000000000200000, 0x00000000002f302c)
Post relocation: addr: 0x00000000000e5c18 memsz: 0x000000000001a3e8 filesz: 0x000000000000db35
using LZMA
[ 0x000e5c18, 00100000, 0x00100000) <- ff83e930
dest 000e5c18, end 00100000, bouncebuffer bfdf9000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 48759 exit 0
Jumping to boot code at 000fd58c
CPU0: stack: 00232000 - 00233000, lowest used address 002325e8, stack used: 2584 bytes
entry    = 0x000fd58c
lb_start = 0x00200000
lb_size  = 0x000f302c
buffer   = 0xbfdf9000
SeaBIOS (version rel-1.7.5-42-g275672e-dirty-20140818_154755-toonie.localdomain)
Found mainboard AMD DB-FT3b
Relocating init from 0x000e6de0 to 0xbff950c0 (size 44672)
Found CBFS header at 0xfffffc50
CPU Mhz=1198
Found 27 PCI devices (max PCI bus is 03)
Copying PIR from 0xbffe0400 to 0x000f1c30
Copying MPTABLE from 0xbffe1400/bffe1410 to 0x000f1a60
Copying ACPI RSDP from 0xbffe2400 to 0x000f1a40
Copying SMBIOS entry point from 0xbffed800 to 0x000f1a20
Using pmtimer, ioport 0x818
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.7.5-42-g275672e-dirty-20140818_154755-toonie.localdomain)
XHCI init on dev 00:10.0: regs @ 0xf0e8a000, 4 ports, 32 slots, 32 byte contexts
XHCI    extcap 0x1 @ f0e8a500
XHCI    protocol USB  3.00, 2 ports (offset 1), def 0
XHCI    protocol USB  2.00, 2 ports (offset 3), def 10
XHCI    extcap 0xa @ f0e8a540
WARNING - Timeout at i8042_flush:71!
EHCI init on dev 00:12.0 (regs=0xf0e8d420)
Found 0 lpt ports
Found 1 serial ports
ATA controller 1 at 3410/3420/0 (irq 0 dev 88)
EHCI init on dev 00:13.0 (regs=0xf0e8d520)
ATA controller 2 at 3418/3424/0 (irq 0 dev 88)
ata0-0: ST3750525AS ATA-8 Hard-Disk (698 GiBytes)
Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0
XHCI no devices found
USB keyboard initialized
Initialized USB HUB (1 ports used)
Initialized USB HUB (0 ports used)
All threads complete.
Scan for option roms
Running option rom at cf00:0003
Searching bootorder for: /pci@i0cf8/pci-bridge@2,1/*@0

Press F12 for boot menu.

Searching bootorder for: HALT
drive 0x000f19d0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1465149168
Space available for UMB: d0000-ef000, f0000-f19d0
Returned 253952 bytes of ZoneHigh
e820 map has 7 items:
  0: 0000000000000000 - 000000000009fc00 = 1 RAM
  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 00000000bffde000 = 1 RAM
  4: 00000000bffde000 - 00000000e0000000 = 2 RESERVED
  5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED
  6: 0000000100000000 - 000000011f000000 = 1 RAM
enter handle_19:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00

Lspci

00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1566
00:01.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Mullins [Radeon APU XX-2450M with R3 Graphics]
00:01.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device 9840
00:02.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 156b
00:02.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1
00:02.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1
00:02.3 PCI bridge: Advanced Micro Devices, Inc. [AMD] Family 16h Processor Functions 5:1
00:08.0 Encryption controller: Advanced Micro Devices, Inc. [AMD] Device 1537
00:10.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 10)
00:11.0 SATA controller: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [IDE mode] (rev 40)
00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 39)
00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 39)
00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller (rev 41)
00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge (rev 11)
00:14.7 SD Host controller: Advanced Micro Devices, Inc. [AMD] FCH SD Flash Controller (rev 01)
00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1580
00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1581
00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1582
00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1583
00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1584
00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1585
01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
02:00.0 Network controller: Broadcom Corporation BCM43225 802.11b/g/n (rev 01)
03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 04)
03:00.1 Serial controller: Realtek Semiconductor Co., Ltd. Device 816a (rev 01)
03:00.2 Serial controller: Realtek Semiconductor Co., Ltd. Device 816b (rev 01)
03:00.3 IPMI SMIC interface: Realtek Semiconductor Co., Ltd. Device 816c (rev 01)

Proprietary BIOS

AMI BIOS is available here. In 'AMIBIOS' choose 'AMD-DB-FT3b Development Board'.

Other issues

S3 Resume

Currently Olive Hill Plus doesn't support S3 resume.