Board:asus/p5gc-mx

From coreboot
Jump to: navigation, search

This page describes how to use coreboot on the Asus p5gc-mx mainboard.

SeaBIOS ATA DMA

By default, SeaBIOS uses PIO mode for ATA interfaces. On the ICH7 southbridge, this is very slow. Loading a kernel + initramfs can take up to 20 seconds on this board.

When using ATA DMA mode, this bug disappears. This will have to be set explicitly in the SeaBIOS config file, and selected from coreboot's menuconfig.

From the coreboot root directory, go to payloads/external/SeaBIOS/seabios:

cd payloads/external/SeaBIOS/seabios/

Create a file called .config and add these lines to it:

CONFIG_COREBOOT=y
CONFIG_ATA_DMA=y
CONFIG_VGA_COREBOOT=y

Then, create a full .config file by running:

make menuconfig

Navigate to General Features and make sure the Build Target is set to Build for coreboot.

Navigate to Hardware support and make sure that ATA DMA is enabled [*].

Navigate to VGA ROM and make sure that VGA Hardware Type is set to coreboot linear framebuffer.

Exit menuconfig and save the changes.


It is probably easiest to move the .config file to the coreboot root directory, under a different name (e.g. .seabiosconfig), as coreboot already has its own .config file.

mv .config ../../../../.seabiosconfig

Finally return to the coreboot root directory:

cd ../../../../

coreboot configuration

Create a file called .config and add at least these lines to it:

CONFIG_VENDOR_ASUS=y
CONFIG_BOARD_ASUS_P5GC_MX=y
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
CONFIG_USE_OPTION_TABLE=y

In case you do not want CPU microcode updates included in your ROM, add this line:

CONFIG_CPU_MICROCODE_CBFS_NONE=y

In case you do want to include CPU microcode updates in your ROM, add these lines:

CONFIG_USE_BLOBS=y
CONFIG_CPU_MICROCODE_CBFS_GENERATE=y

By default, serial debugging output is enabled. It is very useful for debugging, but also slows down the boot process a lot. If you don't need serial debug or have no idea how to use it, disable it:

CONFIG_CONSOLE_SERIAL=n

Then, create a full .config file by running:

make menuconfig

Navigate to General setup and make sure that Use CMOS for configuration values is enabled [*].

Navigate to Mainboard and make sure the Mainboard vendor is set to ASUS and the Mainboard model to P5GC-MX.

Navigate to Chipset and make sure that Include CPU microcode in CBFS is set to either Generate from tree or Do not include microcode updates.

  • In case you selected Generate from tree, make sure that General setup -> Allow use of binary-only repository is enabled [*].

Navigate to Devices and make sure that Use native graphics initialization is enabled [*].

Navigate to Payload and set your SeaBIOS configuration in SeaBIOS config file.

  • This requires a full path. For instance, if your coreboot root directory is in ~/Downloads, set ~/Downloads/coreboot/.seabiosconfig

Exit menuconfig and save the changes.


Now build your ROM:

make

CMOS default values

By default, the VGA shared RAM on this board is set to 8MB. While this is fine for server use, this is not ideal for desktop or HTPC use.

In order to change CMOS defaults, you will need nvramtool:

cd util/nvramtool/
make
mv nvramtool ../../nvramtool
cd ../../

The VGA shared RAM can be increased to 16MB, 32MB or 64MB by running:

./nvramtool -C build/coreboot.rom -w gfx_uma_size=16M

or

./nvramtool -C build/coreboot.rom -w gfx_uma_size=32M

or

./nvramtool -C build/coreboot.rom -w gfx_uma_size=64M

Backing up the vendor BIOS

This board can be flashed from the vendor BIOS with flashrom, which is in the repositories of nearly every GNU/Linux distribution.

To make a backup of the BIOS chip, run:

sudo flashrom -p internal -r bios.rom

Internal flashing

To flash the BIOS chip, run:

sudo flashrom -p internal -w build/coreboot.rom

External flashing

This board has a socketed DIP8 chip, so you can use - for instance - a CH341A to flash it.

Status (as of commit 5bb27b7815)

Device/functionality Status Comments
CPU
CPU works OK Core 2 Duo up to 1067MHz FSB. Pentium 4-like CPUs don't boot.
L1 cache enabled OK
L2 cache enabled OK
L3 cache enabled N/A
Multiple CPU support N/A
Multi-core support OK Quad cores are not supported by the chipset.
Hardware virtualization Untested
RAM
EDO N/A
SDRAM N/A
SO-DIMM N/A
DDR N/A
DDR2 OK
DDR3 N/A
Dual channel support N/A
ECC support N/A
On-board Hardware
On-board IDE 3.5" Untested
On-board IDE 2.5" Untested
On-board SATA OK
On-board SCSI N/A
On-board USB OK
On-board VGA OK VBIOS works. Only textmode available for native graphic init.
On-board Ethernet OK
On-board Audio OK
On-board Modem N/A
On-board FireWire N/A
On-board Smartcard reader N/A
On-board CompactFlash N/A
On-board PCMCIA N/A
On-board Wifi N/A
On-board Bluetooth N/A
On-board SD card reader N/A
Add-on slots/cards
ISA add-on cards N/A
Audio/Modem-Riser (AMR/CNR) cards N/A
PCI add-on cards OK
Mini-PCI add-on cards N/A
Mini-PCI-Express add-on cards Unknown
PCI-X add-on cards N/A
AGP graphics cards N/A
PCI Express x1 add-on cards N/A
PCI Express x2 add-on cards N/A
PCI Express x4 add-on cards N/A
PCI Express x8 add-on cards N/A
PCI Express x16 add-on cards OK
PCI Express x32 add-on cards N/A
HTX add-on cards N/A
Legacy / Super I/O
Floppy Untested
Serial port 1 (COM1) OK
Serial port 2 (COM2) Untested
Parallel port Untested
PS/2 keyboard OK
PS/2 mouse Untested
Game port N/A
Infrared N/A
PC speaker N/A
DiskOnChip N/A
Input
Trackpoint N/A
Touchpad N/A
Fn Hotkeys N/A
Fingerprint Reader N/A
Laptop
Docking VGA N/A
Docking LAN N/A
Docking USB N/A
Docking Audio N/A
Docking Displayport N/A
Thinklight N/A
Webcam N/A
Miscellaneous
Sensors / fan control OK
Hardware watchdog Unknown
SMBus OK
CAN bus N/A
CPU frequency scaling OK
Other powersaving features Unknown
ACPI OK
Reboot OK
Poweroff OK
Suspend OK
Nonstandard LEDs OK
High precision event timers (HPET) Unkown
Random number generator (RNG) N/A
Wake on modem ring Unknown
Wake on LAN Unknown
Wake on keyboard Unknown
Wake on mouse Unknown
TPM Unknown
Flashrom OK Can be flashed from vendor BIOS. Has a DIP8 socket.

Peculiarities

Normally on boards with an LGA755 socket the FSB multiplier is determined by 3 pins/straps on the CPU called BSEL. On this board those pins on the CPU are not hooked up to the memory controller, but some GPIOs on the SuperIO are used instead. The result is that to set up the correct FSB the SuperIO needs to be configured and then the system reset. Since this reset takes a few seconds, the fans will spin up, than spin down again to resume a full boot a few seconds later.

Variants

  • The P5GC-MX/1333 might work just fine with the current code. The P5GC-MX/1333 vendor bios works fine on P5GC-MX but does not configure the SuperIO GPIO BSEL straps correctly which might indicate that it does not have those.
  • P5GC-MX/GBL ?