The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
Intel_Native_Raminit has it's own status page.
|CPU works||OK||Support Ivy Bridge|
|L1 cache enabled||OK||Always on|
|L2 cache enabled||OK||Always on|
|L3 cache enabled||OK||Always on|
|Multiple CPU support||N/A|
|Dual channel support||OK|
|On-board IDE 3.5"||N/A|
|On-board IDE 2.5"||N/A|
|On-board SATA||OK||SATA breaks if me_cleaner is used|
|On-board Audio||OK||external headphones, external mic|
|On-board Smartcard reader||N/A|
|On-board SD card reader||N/A|
|ISA add-on cards||N/A|
|Audio/Modem-Riser (AMR/CNR) cards||N/A|
|PCI add-on cards||N/A|
|Mini-PCI add-on cards||N/A|
|Mini-PCI-Express add-on cards||OK||Half-height mini-PCIe slot works, full-height works either as mSATA or mini-PCIe (select in menuconfig)|
|PCI-X add-on cards||N/A|
|AGP graphics cards||N/A|
|PCI Express x1 add-on cards||N/A|
|PCI Express x2 add-on cards||N/A|
|PCI Express x4 add-on cards||N/A|
|PCI Express x8 add-on cards||N/A|
|PCI Express x16 add-on cards||N/A|
|PCI Express x32 add-on cards||N/A|
|HTX add-on cards||N/A|
|Legacy / Super I/O|
|Serial port 1 (COM1)||OK||Select DRIVERS_UART_8250IO in menuconfig to enable|
|Serial port 2 (COM2)||N/A|
|Sensors / fan control||OK|
|CPU frequency scaling||OK|
|Other powersaving features||N/A|
|Suspend||OK||Suspend to RAM|
|High precision event timers (HPET)||Untested|
|Random number generator (RNG)||Untested|
|Wake on modem ring||N/A|
|Wake on LAN||Untested|
|Wake on keyboard||Untested|
|Wake on mouse||Untested|
- Native graphics init does not produce video output
- No VGA output in SeaBIOS without inclusion of Intel VGA BIOS
- Linux (through SeaBIOS-as-payload)
Proprietary Components Status
- CPU Microcode
- FDT(Flash Descriptor Table) => Always needed
- ME(Management Engine) => you do not have to touch it(just leave it where it is)
- GbE(Gigabit Ethernet embedded mac) => you do not have to touch it(just leave it where it is)
Please have a look at Intel_Sandybridge_Build_Tutorial.
The Intense PC has two 8MB WSON flash chips located on the top of the PCB (facing the upper case). There is no known header, you must solder to the WSON pads. Accessing the flash chips requires complete disassembly of the unit.
FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x0fff0d00 Flash Region 1 (BIOS): 00d00000 - 00ffffff FLREG2: 0x0cff0003 Flash Region 2 (Intel ME): 00003000 - 00cfffff FLREG3: 0x00020001 Flash Region 3 (GbE): 00001000 - 00002fff FLREG4: 0x00001fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
If you are using a hardware SPI flashing tool, remember to split the coreboot.rom file into two 8MB files before attempting to flash:
dd if=build/coreboot.rom of=SC1.bin bs=1M count=8 dd if=build/coreboot.rom of=SC2.bin bs=1M skip=8
If you did not run me_cleaner, then the contents of the "SC1" chip remains unchanged from the vendor firmare and you only need to flash the chip located near "SC2". Any new builds of coreboot only need to be flashed to "SC2"
Flashrom does not support writing to flash with a running ME. Therefore the only way to flash coreboot without disassembling is if the user has NOT updated their firmware to patch CVE-2017-8083 and the flash descriptor table is still allowing writes to BIOS/ME regions. In this situation, the user could theoretically dump the vendor firmware, run me_cleaner, and then flash coreboot without disassembling the unit. This theory has not been tested.
In all other scenarios, there is no way to flash coreboot without disassembling the unit and soldering to the board. Flashing with flashrom may be possible if you are running coreboot without an ME (however this breaks SATA) but this is untested.