Board:compulab/intense pc

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The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to Contributions welcome!


Intel_Native_Raminit has it's own status page.

Device/functionality Status Comments
CPU works OK Support Ivy Bridge
L1 cache enabled OK Always on
L2 cache enabled OK Always on
L3 cache enabled OK Always on
Multiple CPU support N/A
Multi-core support OK
Hardware virtualization OK
DDR3 OK Native
Dual channel support OK
ECC support N/A
On-board Hardware
On-board IDE 3.5" N/A
On-board IDE 2.5" N/A
On-board SATA OK SATA breaks if me_cleaner is used
On-board SCSI N/A
On-board USB OK
On-board VGA OK
On-board Ethernet OK
On-board Audio OK external headphones, external mic
On-board Modem N/A
On-board FireWire N/A
On-board Smartcard reader N/A
On-board CompactFlash N/A
On-board PCMCIA N/A
On-board Wifi N/A
On-board Bluetooth N/A
On-board SD card reader N/A
Add-on slots/cards
ISA add-on cards N/A
Audio/Modem-Riser (AMR/CNR) cards N/A
PCI add-on cards N/A
Mini-PCI add-on cards N/A
Mini-PCI-Express add-on cards OK Half-height mini-PCIe slot works, full-height works either as mSATA or mini-PCIe (select in menuconfig)
PCI-X add-on cards N/A
AGP graphics cards N/A
PCI Express x1 add-on cards N/A
PCI Express x2 add-on cards N/A
PCI Express x4 add-on cards N/A
PCI Express x8 add-on cards N/A
PCI Express x16 add-on cards N/A
PCI Express x32 add-on cards N/A
HTX add-on cards N/A
Legacy / Super I/O
Floppy N/A
Serial port 1 (COM1) OK Select DRIVERS_UART_8250IO in menuconfig to enable
Serial port 2 (COM2) N/A
Parallel port N/A
PS/2 keyboard N/A
PS/2 mouse N/A
Game port N/A
Infrared N/A
PC speaker N/A
DiskOnChip N/A
Trackpoint N/A
Touchpad N/A
Fn Hotkeys N/A
Fingerprint Reader N/A
Docking VGA N/A
Docking LAN N/A
Docking USB N/A
Docking Audio N/A
Docking Displayport N/A
Thinklight N/A
Webcam N/A
Sensors / fan control OK
Hardware watchdog Untested
SMBus Untested
CAN bus N/A
CPU frequency scaling OK
Other powersaving features N/A
Reboot OK
Poweroff OK
Suspend OK Suspend to RAM
Nonstandard LEDs N/A
High precision event timers (HPET) Untested
Random number generator (RNG) Untested
Wake on modem ring N/A
Wake on LAN Untested
Wake on keyboard Untested
Wake on mouse Untested
TPM Absent
Flashrom Unsupported


  • Native graphics init does not produce video output
    • No VGA output in SeaBIOS without inclusion of Intel VGA BIOS

Tested OS

  • Linux (through SeaBIOS-as-payload)

Proprietary Components Status

  • CPU Microcode
  • FDT(Flash Descriptor Table) => Always needed
  • ME(Management Engine) => you do not have to touch it(just leave it where it is)
  • GbE(Gigabit Ethernet embedded mac) => you do not have to touch it(just leave it where it is)

Building Firmware

Please have a look at Intel_Sandybridge_Build_Tutorial.


The Intense PC has two 8MB WSON flash chips located on the top of the PCB (facing the upper case). There is no known header, you must solder to the WSON pads. Accessing the flash chips requires complete disassembly of the unit.

Flash layout:

FLREG0:    0x00000000
  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff 
FLREG1:    0x0fff0d00
  Flash Region 1 (BIOS): 00d00000 - 00ffffff 
FLREG2:    0x0cff0003
  Flash Region 2 (Intel ME): 00003000 - 00cfffff 
FLREG3:    0x00020001
  Flash Region 3 (GbE): 00001000 - 00002fff 
FLREG4:    0x00001fff
  Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)

If you are using a hardware SPI flashing tool, remember to split the coreboot.rom file into two 8MB files before attempting to flash:

dd if=build/coreboot.rom of=SC1.bin bs=1M count=8
dd if=build/coreboot.rom of=SC2.bin bs=1M skip=8

If you did not run me_cleaner, then the contents of the "SC1" chip remains unchanged from the vendor firmare and you only need to flash the chip located near "SC2". Any new builds of coreboot only need to be flashed to "SC2"

Flashrom does not support writing to flash with a running ME. Therefore the only way to flash coreboot without disassembling is if the user has NOT updated their firmware to patch CVE-2017-8083 and the flash descriptor table is still allowing writes to BIOS/ME regions. In this situation, the user could theoretically dump the vendor firmware, run me_cleaner, and then flash coreboot without disassembling the unit. This theory has not been tested.

In all other scenarios, there is no way to flash coreboot without disassembling the unit and soldering to the board. Flashing with flashrom may be possible if you are running coreboot without an ME (however this breaks SATA) but this is untested.