From coreboot
Jump to navigation Jump to search

The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to Contributions welcome!

This page describes using coreboot on the HP Pavilion Chromebook 14.

See Chromebooks for additional details.

General quirks

Flash write-protect

The hardware write protection affects the top 1 MiB of the flash chip. CBFS is stored in this region.

Even though the write-protect switch may be enabled, this does not guarantee that the flash is protected. The write-protection is active when the WP bits are set in the flash chip. flashrom usually disables those bits, and leaves them disabled. The WP bits can be set at any time, but they can only be cleared if the write-protect switch is set to off.

WARNING! Unlike in factory coreboot, in vanilla coreboot, the MRC cache is placed within the write-protected region of flash. Setting the WP bits will make MRC cache read-only. The full effects of this are not well understood, but it seems the system will not be able to suspend. I was not able to make the system crash or hang. It attempts to suspend, but resumes immediately.

Linux quirks

Touchpad issues

The touchpad may or may not be automatically detected. I have seen both cases happen with the same kernel version. The following modules need to be loaded in order for the touchpad to work:

  • i2c-core
  • cyapa
  • chromeos-laptop

In case the touchpad is not detected automatically after these modules are inserted, try to remove and then re-insert chromeos-laptop. Note that chromeos-laptop is not affected by whether or not coreboot was built with "Build for ChromeOS". All these modules are in mainline, so they should be available with any recent distro kernel. To check if the touchpad was detected, look for the following line in the kernel log:

[27158.544831] input: Cypress APA Trackpad (cyapa) as /devices/pci0000:00/0000:00:1f.3/i2c-7/7-0067/input/input14

SMBios motherboard name

The chromeos_laptop kernel module is responsible for detecting and making the touchpad work. The module will refuse to load if the SMBios motherboard is not one of the known models. Hence, the SMBIOS_PRODUCT_NAME needs to contain "Butterfly" for chromeos_laptop to load.

Spurious resume

By default, linux will enable the touchpad buttons as a wakeup source. Since the lid is fairly flexible, gentle pressure will bend it enough to press one of the buttons, resulting in an unwanted resume. Placing the laptop in a backpack or holding it like a book is almost certain to cause a resume. This is a result as the touchpad being declared as a wakeup source in mainboard.asl.

$ cat /proc/acpi/wakeup
Device  S-state   Status   Sysfs node
TPAD      S3    *enabled   pnp:00:00

While, one solution is to hack mainboard.asl, it is also possible to disable the touchpad resume by the following command:

# echo TPAD > /proc/acpi/wakeup

Black screen

The EC allows dimming the display backlight all the way to 0. If the backlight is accidentally set to 0, and the screen is black, try re-plugging the power adapter, or closing and opening the lid. Desktops with power management enabled should automatically adjust the backlight to some sane value. These tricks have been tested with KDE 4.11.

EHCI debug port

With the default settings, the USB port next to the HDMI connector is the EHCI debug port.

Make a backup of the original ROM

With this chromebook, making a backup of the original ROM is highly recommended. Use the usual procedure of entering developer mode and backing up with the built-in flashrom before proceeding.

Building a complete coreboot image

General options

It is recommended to use one of known working configs, but for those who like to tinker, here are some useful hints on getting the most out of coreboot.

The following options will need to be enabled to get a working image:

General setup  --->  [*] Allow use of binary-only repository
Chipset  ---> [*] Add a System Agent binary
Chipset  ---> [*] Add Intel Management Engine firmware

The Video BIOS is available in the blobs repository:

VGA BIOS  ---> [*] Add a VGA BIOS image
VGA BIOS  ---> VGA BIOS path and filename: "3rdparty/mainboard/google/butterfly/snm_2130_coreboot.bin"

It's also a good idea to enable console via CBMEM, while disabling serial and EHCI debug:

Console  ---> [ ] Serial port console output
Console  ---> [ ] USB 2.0 EHCI debug dongle support
Console  ---> [*] Send console output to a CBMEM buffer
Console  ---> [*]   Show POST codes on the debug console

Unless you plan to run ChromeOS, disable ChromeOS features:

ChromeOS  ---> [ ] Build for ChromeOS 

The following options may(TM) make life easier in the future:

General setup  ---> [*] Use CMOS for configuration values
General setup  ---> [*] Create a table of timestamps collected during boot

Including the MAC address and keyboard layout

The coreboot that ships with the laptop will read the keyboard layout and MAC address from the flash. Since ChromeOS uses a different layout than CBFS, the region containing these parameters must me included in the CBFS of the custom coreboot. When not building for ChromeOS, coreboot will read this region from a CBFS file named vpd.bin. NOTE: This will only work when "Build for ChromeOS" is NOT selected. If building for ChromeOS, coreboot will ignore vpd.bin, and try to locate these parameters using fmap.

Get 'flashmap'

$ git clone

Find the RO_VPD section

Build flashmap, then run fmap_decode on the extracted chromebook firmware.

$ ./fmap_decode original_chrome_image.rom

Locate the RO_VPD section in the output:

area_offset="0x00600000" area_size="0x00004000" area_name="RO_VPD" area_flags_raw="0x01" area_flags="static"

Extract the RO_VPD section from ROM image.

First, convert area_offset and area_size to decimal, as dd does not accept hexadecimal input, then use dd to extract the RO_VPD section.

$ dd if=original_chrome_image.rom bs=1 skip=ibs=$((area_offset)) count=$((area_size)) of=vpd.bin

(Optional) Strip down vpd.bin

The vpd.bin is a 16KiB file, most of which is all 1's, and only a subset of the information is used by coreboot. To save down on flash usage, it's possible to remove all but the non-essential parts with a hex editor. See example vpd.bin hexdumps to get an idea of what information can be stripped. The vpd.bin can be reduced to under 300 bytes.

Insert vpd.bin in the custom coreboot image:

$ cbfstool build/coreboot.rom add -f vpd.bin -n vpd.bin -t raw

Useful unmerged patches

This is a list of useful coreboot patches that have either been rejected for bureaucratic reasons, or just not yet merged.

  • Remove 3Gbps SATA speed limit link

Possible hardware upgrades

Luckily, the Pavilion Chromebook 14 is an older generation where not all components are tightly integrated. As a result, this Chromebook is reasonably upgradeable.

Storage upgrade

The SSD has a standard SATA data+power connector (SFF-8482). As a result, the drive can be replaced with any 2.5" drive that is 10mm high or slimmer.

RAM upgrade

This Chromebook comes with 2 SODIMM slots. The first slot is populated, and the second one is free.

Channel layout

Each slot is connected to a separate memory channel. This laptop is dual-channel capable if upgraded. It comes with only one DIMM, so it operates in single channel by default.

Rank layout

Each slot has been verified to boot successfully with dual-rank DIMMs (16 dram chips). The following table lists the tested 2-DIMM combinations in green, and untested in yellow.

Ranks x1 x2
x1 OK OK
x2 OK ??

Maximum RAM

In theory, the memory controller on the Celeron 847 CPU supports 16 GiB. This Chromebook has been tested with up to 8GiB (2x4GiB DIMMs). It is unclear if 8 GiB DIMMs are supported, and if a 2x8GiB arrangement will yield 16 GiB of usable DRAM (minus framebuffer).

DDR3 speed

The memory controller is limited to DDR3-1333. DDR3-1333 and faster DIMMs will be limited to 1333 MHz by the memory controller.

Low-Voltage (1.35V) DIMM support

It is unclear (and untested) if this Chromebook will run low-voltage capable DIMMs at 1.35V instead of 1.5V. According to the coreboot source, it will not, but it is unclear whether enabling the LV support bit will run the DIMMs at 1.35V.