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(Created page with "Full name: Jonathan Neuschäfer ==GSoC 2016== During this year's Google Summer of Code, I'm working on improving coreboot's support for RISC-V systems. This involves: - Get...") |
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This involves: | This involves: | ||
* Getting coreboot to run on [[Board:emulation/spike-riscv|SPIKE]] (somewhat done, on an outdated version of SPIKE) | |||
* Getting coreboot+Linux to run on SPIKE | |||
* Getting coreboot to run on an FPGA/Softcore platform | |||
* Getting coreboot+Linux to run on an FPGA | |||
* Implementing additional features | |||
** e.g. libpayload support, CBMEM, vboot, FreeBSD compatibility, ... | |||
* Bugfixes whenever something RISC-V related needs to be fixed | |||
Revision as of 11:22, 31 May 2016
Full name: Jonathan Neuschäfer
GSoC 2016
During this year's Google Summer of Code, I'm working on improving coreboot's support for RISC-V systems. This involves:
- Getting coreboot to run on SPIKE (somewhat done, on an outdated version of SPIKE)
- Getting coreboot+Linux to run on SPIKE
- Getting coreboot to run on an FPGA/Softcore platform
- Getting coreboot+Linux to run on an FPGA
- Implementing additional features
- e.g. libpayload support, CBMEM, vboot, FreeBSD compatibility, ...
- Bugfixes whenever something RISC-V related needs to be fixed