User:Jn: Difference between revisions
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<tr><td>Name:</td><td></td></tr> | |||
<tr><td>IRC (Freenode):</td><td>jn__</td></tr> | |||
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==GSoC 2016== | ==GSoC 2016== | ||
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This involves: | This involves: | ||
* Getting coreboot to run on [[Board:emulation/spike-riscv|SPIKE]] ( | * Getting coreboot to run on [[Board:emulation/spike-riscv|SPIKE]] (done) | ||
* Getting coreboot+Linux to run on SPIKE | * Getting coreboot+Linux to run on SPIKE (somewhat done) | ||
* Getting coreboot to run on an FPGA/Softcore platform | * Getting coreboot to run on an FPGA/Softcore platform | ||
* Getting coreboot+Linux to run on an FPGA | * Getting coreboot+Linux to run on an FPGA | ||
Latest revision as of 21:52, 29 June 2016
| Name: | Jonathan Neuschäfer |
| IRC (Freenode): | jn__ |
GSoC 2016
During this year's Google Summer of Code, I'm working on improving coreboot's support for RISC-V systems. This involves:
- Getting coreboot to run on SPIKE (done)
- Getting coreboot+Linux to run on SPIKE (somewhat done)
- Getting coreboot to run on an FPGA/Softcore platform
- Getting coreboot+Linux to run on an FPGA
- Implementing additional features
- e.g. libpayload support, CBMEM, vboot, FreeBSD compatibility, ...
- Bugfixes whenever something RISC-V related needs to be fixed
I'm writing weekly blog posts at https://blogs.coreboot.org