[coreboot-gerrit] New patch to review for coreboot: arch/riscv: Add misc.c to bootblock/romstage to get udelay()

[Jonathan Neuschäfer (j.neuschaefer@gmx.net)]

Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15147

-gerrit

commit 8eec1757221be39a89606d33bf6b3edbaea9dc4e
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Fri Jun 10 19:35:15 2016 +0200

    arch/riscv: Add misc.c to bootblock/romstage to get udelay()
    
    The uart8250mem driver needs it.
    
    Change-Id: I09e6a17cedf8a4045f008f5a0d225055d745e8db
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
 src/arch/riscv/Makefile.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 6784d9b..4521dcb 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -34,6 +34,7 @@ bootblock-y += trap_handler.c
 bootblock-y += virtual_memory.c
 bootblock-y += boot.c
 bootblock-y += rom_media.c
+bootblock-y += misc.c
 bootblock-y += \
 	$(top)/src/lib/memchr.c \
 	$(top)/src/lib/memcmp.c \
@@ -57,6 +58,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
 romstage-y += boot.c
 romstage-y += stages.c
 romstage-y += rom_media.c
+romstage-y += misc.c
 romstage-y += \
 	$(top)/src/lib/memchr.c \
 	$(top)/src/lib/memcmp.c \