[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Implement Global Reset MEI message

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit ff8bf410d9596ac82b183cb62e2d8990c550ee4a
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Fri Aug 19 12:33:42 2016 +0530

    soc/intel/skylake: Implement Global Reset MEI message
    
    As per ME BWG, there are two mechanism to generate a Global
    Reset (resets both host and Intel ME), one is through CF9h
    IO write of 6h or Eh with "CF9h Global Reset" (CF9GR) bit set,
    PMC PCI offset ACh[20]. Another is to issue the Global Reset
    MEI message. Because any attempts to cause global reset without
    synchronizing the two sides might cause unwanted side effects,
    such as unwritten flash data that will get destroyed if the
    host were to cause a global reset without informing Intel ME
    firmware, the recommended method is to send a Global Reset MEI
    message when the following conditions are met:
    
    The PCH chipset firmware just needs to complete the Intel ME
    Interface #1 initialization and check the Intel ME HFSTS state
    if Intel ME is not in ERROR state and is accepting MEI commands
    then firmware should be able to use Global Reset MEI message to
    trigger global reset.
    
    Furthermore, if Intel ME is in ERROR state, BIOS can use I/O 0xCF9
    write of 0x06 or 0x0E command with PCH ETR3 register bit [20]
    to perform the global reset.
    
    BUG=none
    BRANCH=none
    TEST=Verified Global Reset MEI message is able to perform platform
    global issue in ME good state.
    
    Change-Id: If326a137eeadaa695668b76b84c510e12c546024
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Reviewed-on: https://review.coreboot.org/16902
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/16902 for details.

-gerrit